By Wen-Yee Lee
HSINCHU, Taiwan, May 14 (Reuters) - TSMC, the world's largest contract chipmaker, expects the global semiconductor market to exceed $1.5 trillion by 2030, topping its previous forecast of $1 trillion, according to its presentation materials ahead of a tech symposium on Thursday.
Here are the details:
• AI and high-performance computing are expected to account for 55% of the $1.5 trillion market, followed by smartphones with 20%, and automotive applications with 10%, according to TSMC.
• TSMC said it has been expanding capacity at a faster pace in 2025 and 2026 and plans to build nine phases of wafer fabs and advanced packaging facilities in 2026.
• The chipmaker is projected to ramp up capacity for its most advanced 2-nanometer and next generation A16 chips, with a compounded annual growth rate (CAGR) of 70% from 2026 to 2028.
• TSMC said CAGR of capacity for its advanced packaging CoWoS (Chip on Wafer on Substrate) is forecast at more than 80% from 2022 to 2027. CoWoS is a key chip packaging technology widely used in AI chips including those designed by Nvidia.
• The company said AI accelerator wafer demand is projected to increase 11-fold from 2022 to 2026.
TSMC'S GLOBAL FOOTPRINT
• Arizona: The first fab is already in production. Tool move-in for the second fab is planned for the second half of 2026. Construction of a third fab is underway. Work on a fourth fab and the site's first advanced packaging facility is expected to begin this year.
• TSMC anticipates a 1.8-fold year-on-year increase in Arizona output by 2026, with yields comparable to those in Taiwan.
• The chipmaker said it completed the purchase of a second large parcel of land in Arizona for future expansion.
• Japan: The first fab is currently in volume production for 22-nanometer and 28-nanometer products. Plans for the second fab have been upgraded to 3-nanometer in response to strong demand.
• Germany: The fab is currently under construction and progressing as scheduled. It plans to provide 28-nanometer and 22-nanometer technologies, followed by 16-nanometer and 12-nanometer technologies.
(Reporting by Wen-Yee Lee; Editing by Kate Mayberry)
